MCBSTM32EXL【PDF 510/995 页】BOARD EVALUATION FOR STM32F103ZE

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Secure digital input/output interface (SDIO)

RM0008

20.9.15

SDIO data FIFO register (SDIO_FIFO)

Address offset: 0x80

Reset value: 0x0000 0000

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs

contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store

multiple operands to read from/write to the FIFO.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

FIF0Data

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

bits 31:0 FIFOData: Receive and transmit FIFO data

The FIFO data occupies 32 entries of 32-bit words, from address:

SDIO base + 0x080 to SDIO base + 0xFC.

20.9.16

SDIO register map

The following table summarizes the SDIO registers.

Table 151. SDIO register map

Offset

0x00

0x04

Register

SDIO_POWER

SDIO_CLKCR

0x08

0x0C

SDIO_ARG

SDIO_CMD

CMDARG

0x10

0x14

0x18

0x1C

0x20

0x24

SDIO_RESPCM

D

SDIO_RESP1

SDIO_RESP2

SDIO_RESP3

SDIO_RESP4

SDIO_DTIMER

Reserved

CARDSTATUS1

CARDSTATUS2

CARDSTATUS3

CARDSTATUS4

DATATIME

RESPCMD

0x28

0x2C

0x30

SDIO_DLEN

SDIO_DCTRL

SDIO_DCOUNT

Reserved

Reserved

DATALENGTH

DATACOUNT

0x34

510/995

SDIO_STA

Doc ID 13902 Rev 9

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